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| PRELIMINARY CY2305C CY2309C 3.3V Zero Delay Clock Buffer Features 10 MHz to 100-133 MHz operating range, compatible with CPU and PCI bus frequencies Zero input and output propagation delay Multiple low skew outputs One input drives five outputs (CY2305C) One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C) 50 ps typical cycle-cycle jitter (15 pF, 66 MHz) Test Mode to bypass phase locked loop (PLL) (CY2309C) only, see "Select Input Decoding for CY2309C" on page 3 Available in space saving 16-pin 150 Mil SOIC or 4.4 mm TSSOP packages (CY2309C), and 8-pin, 150 Mil SOIC package (CY2305C) 3.3V operation Industrial temperature available CY2309C. It accepts one reference input and drives out five low skew clocks. The -1H versions of each device operate up to 100-133 MHz frequencies and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY2309C has two banks of four outputs each that are controlled by the select inputs as shown in the "Select Input Decoding for CY2309C" on page 3. If all output clocks are not required, BankB is three-stated. The input clock is directly applied to the outputs by the select inputs for chip and system testing purposes. The CY2305C and CY2309C PLLs enter a power down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off. This results in less than 12.0 A of current draw for commercial temperature devices and 25.0 A for industrial temperature parts. The CY2309C PLL shuts down in one additional case as shown in the "Select Input Decoding for CY2309C" on page 3. In the special case when S2:S1 is 1:0, the PLL is bypassed and REF is output from DC to the maximum allowable frequency. The part behaves like a non-zero delay buffer in this mode and the outputs are not three-stated. The CY2305C or CY2309C is available in two or three different configurations as shown in the "Ordering Information" on page 11. The CY2305C-1 or CY2309C-1 is the base part. The CY2305-1H or CY2309-1H is the high drive version of the -1. Its rise and fall times are much faster than the -1s. Functional Description The CY2305C and CY2309C are die replacement parts for CY2305 and CY2309. The CY2309C is a low cost 3.3V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305C is an 8-pin version of the Logic Block Diagram for CY2309C PLL REF MUX CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 Select Input Decoding S1 CLKB2 CLKB3 CLKB4 S2 Cypress Semiconductor Corporation Document Number: 38-07672 Rev. *F * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised July 5, 2007 [+] Feedback PRELIMINARY CY2305C CY2309C Logic Block Diagram for CY2305C REF PLL CLKOUT CLK1 CLK2 CLK3 CLK4 Document Number: 38-07672 Rev. *F Page 2 of 14 [+] Feedback PRELIMINARY CY2305C CY2309C Pinouts CY2309C Figure 1. Pin Diagram - 16 Pin SOIC/TSSOP SOIC/TSSOP Top View REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CY2309C CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 Table 1. Pin Definition - 16 Pin SOIC/TSSOP Pin Signal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF[1] CLKA1[2] CLKA2[2] VDD GND CLKB1[2] CLKB2[2] S2[3] S1[3] CLKB3[2] CLKB4[2] GND VDD CLKA3[2] CLKA4[2] CLKOUT[2] Input reference frequency Buffered clock output, Bank A Buffered clock output, Bank A 3.3V supply Ground Buffered clock output, Bank B Buffered clock output, Bank B Select input, bit 2 Select input, bit 1 Buffered clock output, Bank B Buffered clock output, Bank B Ground 3.3V supply Buffered clock output, Bank A Buffered clock output, Bank A Description Buffered output, internal feedback on this pin Table 2. Select Input Decoding for CY2309C S2 0 0 1 1 S1 0 1 0 1 CLOCK A1-A4 Three state Driven Driven Driven CLOCK B1-B4 Three state Three state Driven Driven CLKOUT[4] Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Shutdown N N Y N Notes 1. Weak pull down. 2. Weak pull down on all outputs. 3. Weak pull ups on these inputs. 4. This output is driven and has an internal feedback for the PLL. The load on this output is adjusted to change the skew between the reference and output. Document Number: 38-07672 Rev. *F Page 3 of 14 [+] Feedback PRELIMINARY CY2305C CY2309C CY2305C Figure 2. Pin Diagram - 8 Pin SOIC SOIC Top View REF CLK2 CLK1 GND 1 2 3 4 CY2305C 8 7 6 5 CLKOUT CLK4 V DD CLK3 Table 3. Pin Description - 8 Pin SOIC Pin 1 2 3 4 5 6 7 8 REF[1] CLK2[2] CLK1[2] GND CLK3[2] VDD CLK4[2] CLKOUT[2] Signal Input reference frequency Buffered clock output Buffered clock output Ground Buffered clock output 3.3V supply Buffered clock output Buffered clock output, internal feedback on this pin Description Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input or output delay. For applications requiring zero input or output delay, all outputs including CLKOUT are equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs for obtaining zero input or output delay. For zero output or output skew, all outputs are loaded equally. For further information refer to the application note entitled "CY2305 and CY2309 as PCI and SDRAM Buffers". Document Number: 38-07672 Rev. *F Page 4 of 14 [+] Feedback PRELIMINARY CY2305C CY2309C Absolute Maximum Conditions Supply Voltage to Ground Potential................-0.5V to +4.6V DC Input Voltage (Except REF) ............ -0.5V to VDD + 0.5V DC Input Voltage REF ........................... -0.5V to VDD + 0.5V Storage Temperature ................................. -65C to +150C Junction Temperature ................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ........................... > 2,000V Operating Conditions for CY2305CSXC-XX and CY2309CSXC-XX Operating Conditions table for CY2305CSXC-XX and CY2309CSXC-XX Commercial Temperature Devices. Parameter VDD TA CL CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance Power up time for all VDDs to reach minimum specified voltage (power ramps are monotonic) 0.05 Description Min 3.0 0 Max 3.6 70 30 10 7 50 Unit V C pF pF pF ms Electrical Characteristics for CY2305CSXC-XX and CY2309CSXC-XX Electrical Characteristics table for CY2305CSXC-XX and CY2309CSXC-XX Commercial Temperature Devices. Parameter VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Input LOW Input HIGH Voltage[5] Voltage[5] VIN = 0V VIN = VDD IOL = 8 mA (-1) IOH = 12 mA (-1H) IOH = -8 mA (-1) IOL = -12 mA (-1H) REF = 0 MHz Unloaded outputs at 66.67 MHz, SEL inputs at VDD Test Conditions Min -0.3 2.0 - - - 2.4 - - Max 0.8 VDD + 0.3 50 100 0.4 - 12.0 32 Unit V V A A V V A mA Input LOW Current Input HIGH Current Output LOW Voltage[6] Output HIGH Voltage[6] Power Down Supply Current Supply Current Notes 5. .REF input has a threshold voltage of VDD/2. 6. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document Number: 38-07672 Rev. *F Page 5 of 14 [+] Feedback PRELIMINARY CY2305C CY2309C Switching Characteristics for CY2305CSXC-XX and CY2309CSXC-XX Switching characteristics table for CY2305CSXC-1 and CY2309CSXC-1 Commercial Temperature Devices. All parameters are specified with loaded outputs. Parameter Name Test Conditions Min Typ Max Unit t1 Output Frequency Duty Cycle[6] = t2 / t1 t3 t4 t5 t6A t6B t7 tJ tLOCK Rise Time [6] 30 pF load 10 pF load Measured at 1.4V, Fout = 66.67 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V [6] 10 10 40.0 - - - - 1 - - - - 50.0 - - - 0 5 0 50 - 100 133.33 60.0 2.25 2.25 200 350 8.7 700 175 1.0 MHz MHz % ns ns ps ps ns ps ps ms Fall Time[6] Output to Output Skew All outputs equally loaded Delay, REF Rising Edge to Measured at VDD/2 CLKOUT Rising Edge[6] Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL CLKOUT Rising Edge[6] Bypass Mode, CY2309C device only. Device to Device Skew[6] Measured at VDD/2 on the CLKOUT pins of devices Stable power supply, valid clock presented on REF pin Cycle to Cycle Jitter, peak[6] Measured at 66.67 MHz, loaded outputs PLL Lock Time[6] Switching characteristics table for CY2305CSXC-1H and CY2309CSXC-1H Commercial Temperature Devices. All parameters are specified with loaded outputs. Parameter t1 Name Output Frequency Duty Cycle[6] = t2 / t1 Duty Cycle[6] = t2 / t1 t3 t4 t5 t6A t6B t7 t8 tJ tLOCK Rise Time[6] Skew[6] Fall Time[6] Output to Output 30-pF load 10-pF load Measured at 1.4V, Fout = 66.67 MHz Measured at 1.4V, Fout < 50.0 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V All outputs equally loaded Description Min 10 10 40.0 45.0 - - - - 1 - 1 - - Typ - 50.0 50.0 - - - 0 5 0 - - - Max 100 133.33 60.0 55.0 1.5 1.5 200 350 8.7 700 - 175 1.0 Unit MHz MHz % % ns ns ps ps ns ps V/ns ps ms Delay, REF Rising Edge to Measured at VDD/2 CLKOUT Rising Edge[6] Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL CLKOUT Rising Edge[6] Bypass Mode, CY2309C device only. Device to Device Skew[6] Output Slew Rate[6] Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8V and 2.0V using Test Circuit #2 Stable power supply, valid clock presented on REF pin Cycle to Cycle Jitter, peak[6] Measured at 66.67 MHz, loaded outputs PLL Lock Time [6] Document Number: 38-07672 Rev. *F Page 6 of 14 [+] Feedback PRELIMINARY CY2305C CY2309C Operating Conditions for CY2305CSXI-XX and CY2309CSXI-XX Operating conditions table for CY2305CSXI-XX and CY2309CSXI-XX Industrial Temperature Devices. Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance Description Min 3.0 -40 - - - Max 3.6 85 30 10 7 Unit V C pF pF pF Electrical Characteristics for CY2305CSXI-XX and CY2309CSXI-XX Electrical characteristics table for CY2305CSXI-XX and CY2309CSXI-XX Industrial Temperature Devices. Parameter VIL VIH IIL IIH VOL VOH Description Input LOW Voltage[5] Input HIGH Voltage[5] VIN = 0V VIN = VDD IOL = 8 mA (-1) IOH =12 mA (-1H) IOH = -8 mA (-1) IOL = -12 mA (-1H) REF = 0 MHz Unloaded outputs at 66.67 MHz, SEL inputs at VDD Input LOW Current Input HIGH Current Output LOW Voltage[6] Output HIGH Voltage[6] Test Conditions Min -0.3 2.0 - - - 2.4 - - Max 0.8 VDD + 0.3 50.0 100.0 0.4 - 25.0 35 Unit V V A A V V A mA IDD (PD mode) Power down Supply Current IDD Supply Current Document Number: 38-07672 Rev. *F Page 7 of 14 [+] Feedback PRELIMINARY CY2305C CY2309C Switching Characteristics for CY2305CSXI-XX and CY2309CSXI-XX Switching characteristics table for CY2305CSXI-1and CY2309CSXI-1 Industrial Temperature Devices. All parameters are specified with loaded outputs. Parameter t1 Name Output Frequency Duty Cycle[6] = t2 / t1 t3 t4 t5 t6A t6B Rise Time[6] Fall Time[6] Output to Output Skew[6] Delay, REF Rising Edge to CLKOUT Rising Edge[6] Delay, REF Rising Edge to CLKOUT Rising Edge[6] Device to Device Skew[6] Test Conditions 30 pF load 10 pF load Measured at 1.4V, Fout = 66.67 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V All outputs equally loaded Measured at VDD/2 Measured at VDD/2. Measured in PLL Bypass Mode, CY2309C device only. Measured at VDD/2 on the CLKOUT pins of devices Min 10 10 40.0 - - - - 1 50.0 - - - 0 5 Typ Max 100 133.33 60.0 2.25 2.25 200 350 8.7 Unit MHz MHz % ns ns ps ps ns t7 tJ tLOCK - - - 0 50 - 700 175 1.0 ps ps ms Cycle to Cycle Jitter, peak[6] Measured at 66.67 MHz, loaded outputs PLL Lock Time[6] Stable power supply, valid clock presented on REF pin Switching characteristics table for CY2305CSXI-1H and CY2309CSXI-1H Industrial Temperature Device. All parameters are specified with loaded outputs. Parameter t1 Name Output Frequency Duty Cycle[6] = t2 / t1 Duty Cycle[6] = t2 / t1 t3 t4 t5 t6A t6B Rise Time[6] [6] Description 30 pF load 10 pF load Measured at 1.4V, Fout = 66.67 MHz Measured at 1.4V, Fout < 50.0 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V All outputs equally loaded Measured at VDD/2 Measured at VDD/2. Measured in PLL Bypass Mode, CY2309C device only. Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8V and 2.0V using Test Circuit #2 Min 10 10 40.0 45.0 - - - - 1 Typ - 50.0 50.0 - - - 0 5 Max 100 133.33 60.0 55.0 1.5 1.5 200 350 8.7 Unit MHz MHz % % ns ns ps ps ns Fall Time[6] Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge[6] Delay, REF Rising Edge to CLKOUT Rising Edge[6] Device to Device Skew[6] Output Slew Rate[6] t7 t8 tJ tLOCK - 1 - - 0 - - - 700 ps V/ns Cycle to Cycle Jitter, peak[6] Measured at 66.67 MHz, loaded outputs PLL Lock Time[6] Stable power supply, valid clock presented on REF pin 175 1.0 ps ms Document Number: 38-07672 Rev. *F Page 8 of 14 [+] Feedback PRELIMINARY CY2305C CY2309C Switching Waveforms Figure 3. Duty Cycle Timing t1 t2 1.4V 1.4V 1.4V Figure 4. All Outputs Rise/Fall Time 3.3V 0V OUTPUT 2.0V 0.8V t3 2.0V 0.8V t4 Figure 5. Output-Output Skew 1.4V OUTPUT OUTPUT t5 1.4V Figure 6. Input-Output Propagation Delay INPUT VDD/2 OUTPUT t6 VDD/2 Figure 7. Device-Device Skew VDD/2 CLKOUT, Device 1 CLKOUT, Device 2 t7 VDD/2 Document Number: 38-07672 Rev. *F Page 9 of 14 [+] Feedback PRELIMINARY CY2305C CY2309C Test Circuits Test Circuit # 1 V DD 0.1 F CLK OUTPUTS C LOAD V DD 0.1 F GND GND 0.1 F V DD GND GND out 0.1 F Test Circuit # 2 V DD OUTPUTS 10 pF 1 k 1 k For parameter t8 (output slew rate) on -1H devices Document Number: 38-07672 Rev. *F Page 10 of 14 [+] Feedback PRELIMINARY CY2305C CY2309C Ordering Information Ordering Code Pb-Free - CY2305C CY2305CSXC-1 CY2305CSXC-1T CY2305CSXC-1H CY2305CSXC-1HT CY2305CSXI-1 CY2305CSXI-1T CY2305CSXI-1H CY2305CSXI-1HT Pb-Free- CY2309C CY2309CSXC-1 CY2309CSXC-1T CY2309CSXC-1H CY2309CSXC-1HT CY2309CSXI-1 CY2309CSXI-1T CY2309CSXI-1H CY2309CSXI-1HT CY2309CZXC-1 CY2309CZXC-1T CY2309CZXC-1H CY2309CZXC-1HT CY2309CZXI-1 CY2309CZXI-1T CY2309CZXI-1H CY2309CZXI-1HT 16-pin 150 Mil SOIC 16-pin 150 Mil SOIC - Tape and Reel 16-pin 150 Mil SOIC 16-pin 150 Mil SOIC - Tape and Reel 16-pin 150 Mil SOIC 16-pin 150 Mil SOIC - Tape and Reel 16-pin 150 Mil SOIC 16-pin 150 Mil SOIC - Tape and Reel 16-pin 4.4 mm TSSOP 16-pin 4.4 mm TSSOP - Tape and Reel 16-pin 4.4 mm TSSOP 16-pin 4.4 mm TSSOP - Tape and Reel 16-pin 4.4 mm TSSOP 16-pin 4.4 mm TSSOP - Tape and Reel 16-pin 4.4 mm TSSOP 16-pin 4.4 mm TSSOP - Tape and Reel Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial 8-pin 150 Mil SOIC 8-pin 150 Mil SOIC - Tape and Reel 8-pin 150 Mil SOIC 8-pin 150 Mil SOIC - Tape and Reel 8-pin 150 Mil SOIC 8-pin 150 Mil SOIC - Tape and Reel 8-pin 150 Mil SOIC 8-pin 150 Mil SOIC - Tape and Reel Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Package Type Operating Range Document Number: 38-07672 Rev. *F Page 11 of 14 [+] Feedback PRELIMINARY CY2305C CY2309C Package Drawing and Dimensions Figure 8. 8-Pin (150 Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG. 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] Figure 9. 16-Pin (150 Mil) SOIC S16 PIN 1 ID 8 1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] PACKAGE WEIGHT 0.15gms PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 9 16 0.386[9.804] 0.393[9.982] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] Document Number: 38-07672 Rev. *F Page 12 of 14 [+] Feedback PRELIMINARY CY2305C CY2309C Figure 10. 16-Pin TSSOP 4.40 MM Body Z16.173 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] PACKAGE WEIGHT 0.05gms 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0-8 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 4.90[0.193] 5.10[0.200] Document Number: 38-07672 Rev. *F Page 13 of 14 [+] Feedback PRELIMINARY CY2305C CY2309C Document History Page Document Title: CY2305C CY2309C 3.3V Zero Delay Clock Buffer Document Number: 38-07672 REV. ** *A *B *C *D *E *F ECN NO. 224421 268571 276453 303063 318315 344815 1279889 Issue Date See ECN See ECN See ECN See ECN See ECN See ECN See ECN Orig. of Change RGL RGL RGL RGL RGL RGL KVM New datasheet Added bullet for 5V tolerant inputs in the features Minor Change: Moved one sentence from the features to the Functional Description Updated datasheet as per characterization data Datasheet rewrite Minor Error: Corrected the header of all the AC/DC tables with the right part numbers. Changed title from "Low Cost 3.3V Zero Delay Buffer" to "3.3V Zero Delay Clock Buffer" Specified the VIL minimum value to -0.3V Specified the VIH maximum value to VDD + 0.3V Changed DC Input Voltage (REF) maximum value in Absolute Maximum section Removed references to 5V tolerant inputs (pages 1 and 2) Removed Pentium compatibility reference Added CY2305C block diagram Added "peak" to the jitter specifications Changed typical jitter from 75 ps to 50 ps for standard drive devices For standard drive devices, tightened rise/fall times from 2.5 ns to 2.25 ns Tightened cycle-to-cycle jitter from 200 ps to 175 ps Tightened output-to-output skew from 250 ps to 200 ps Description of Change (c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07672 Rev. *F Revised July 5, 2007 Page 14 of 14 PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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